In a circuit consisting of P- and N-type FETs (Field Effect Transistors), a condition called a ‘drive fight’ can exist when both a P-FET and an N-FET that share a common net connection are turned on, thus creating a path from a voltage rail (e.g., VDD) to ground. This drive fight is undesirable from a power consumption standpoint, since it means that current essentially flows directly from the positive supply rail to the negative one through the FETs, and is therefore a waste of current. Both the P-FET and N-FET may be a stack of channel connected FETs, as long as the stacks share a common node. One way to avoid drive fights is to use complementary FET logic, which means that for every P-FET in the logic gate, there is an N-FET that shares the same input signal, such that when the P-FET is on, the N-FET is off, and vice versa. This complementary FET logic prevents drive fight conditions. However, complementary (e.g., CMOS) logic can be slow, so ‘dynamic logic’ may be employed to enhance circuit performance. Dynamic logic basically consists of a P-FET that pulls the output of the logic gate high, and some sort of tree of N-FETs connected to the P-FET that can pull the node low if necessary. A problem with dynamic logic is that if there is no corresponding N-FET in each branch of the tree for each P-FET, then a drive fight condition results. Therefore, what is needed is a method for identifying situations where a drive fight can occur, and also for determining the amount of current that the drive fight sinks.